1. Field of the Invention
The invention relates to an electronic elements arrangement method, and more particularly to a method for arranging electronic elements in an integrated circuit (IC) layout.
2. Description of the Related Art
A voltage controlled oscillator (VCO) typically comprises an odd number of inverters. The delay time of each inverter is utilized to generate an oscillating waveform of the VCO. If the number of inverters of the VCO is N, the period is 2N×tp and the oscillation frequency is
      1          2      ⁢      N      ×              t        p              ,      t    p  being a propagation delay. The described inverters are controlled by input voltage from an input terminal to generate internal frequency oscillation. An output frequency is then generated at the output terminal.
FIG. 1 shows an integrated circuit (IC) layout schematic diagram of a conventional VCO with various inverters. As shown in FIG. 1, a conventional VCO comprises seven sequential inverters 121-127, first-seventh. Each inverter of seven inverters 121-127 comprises an input terminal 1211, 1221, 1231, 1241, 1251, 1261 and 1271 respectively and an output terminal 1212, 1222, 1232, 1242, 1252, 1262 and 1272 respectively. The inverters are connected in the manner described in the following. Output terminal 1212 of the first inverter 121 is coupled to input terminal 1221 of the second inverter 122. Output terminal 1222 of the second inverter 122 is coupled to input terminal 1231 of the third inverter 123. Output terminal 1232 of the third inverter 123 is coupled to input terminal 1241 of the fourth inverter 124. Output terminal 1242 of the fourth inverter 124 is coupled to input terminal 1251 of the fifth inverter 125. Output terminal 1252 of the fifth inverter 125 is coupled to input terminal 1261 of the sixth inverter 126. Output terminal 1262 of the sixth inverter 126 is coupled to input terminal 1271 of the seventh inverter 127; and output terminal 1272 of the seventh inverter 127 is coupled to input terminal 1211 of the first inverter 121, thus completing the VCO for generating frequency oscillation.
The connection between elements within the IC generates parasitic capacitance and parasitic resistance, thus the characteristics of the electronic element, such as the characteristics of the resistors and capacitors may be affected. As shown in FIG. 1, a conductive line coupled between the output terminal 1272 of the seventh inverter 127 and the input terminal 1211 of the first inverter 121 is longer than other conductive lines. Thus, the parasitic resistance generated in the conductive line coupled between the output terminal 1272 of the seventh inverter 127 and the input terminal 1211 of the first inverter 121 is different than that generated in other conductive lines. The phase offset thus causes a different delay in the signal of each inverter. If the VCO has a variety of inverters, the characteristics of the VCO are affected generating phase difference and frequency offset because the output characteristics of various inverters depend on the arrangement of electronic elements in the IC layout.
Thus, a VCO with stable output frequency is desirable.